Electronic devices are generally power supplied so as to achieve their respective functions and thus the respective power associated circuits therefor are indispensable. For real use, a “reset” function is generally provided for the power operation so that a user may “soft” or “hard” power on and off the electronic device, e.g. the user may reset a computer. The soft power on operation means that the electronic device is reset upon receiving a power on reset signal with the presence of the power. The hard power on operation means that the electronic device is reset upon receiving a power on reset signal, with the power previously forced to be shut off. The electronic device is power on reset not immediately after the power reset signal but after the power on reset signal is transitioned from a disactivated state to an activated state. However, the power on reset signal can not be assured to generate stably when the electronic device is hard powered on. The unstable generation of the power on reset signal may be ascribed to a slow rising speed, noises and level switching of the direct current (DC) power voltage.
Referring to FIGS. 1A and 1B, a conventional power reset signal generation circuit and its signal wave plot are respectively shown therein. As shown, a power voltage Vdd is supplied to the circuit and the power voltage Vdd charges a resistor R and a capacitor C. Then, a voltage on the capacitor C outputs a power on reset signal POR via a buffer B. Since the power voltage Vdd does not take the form of an ideal step wave, a ramp signal is presented before the power voltage Vdd rises to its nominal value. At this time, the power on reset signal POR is not in its activated state and is in a low level state in this case. When the voltage of a node A rises continuously before a specific value is reached (refer to the waveform VA), the power on reset signal is still presented as the low level state, meaning the whole circuit is resetting a corresponding electronic device (not shown). When the voltage of the node A is charged up to the specific value, the power on reset signal POR is changed to an activated level (high level in this case), meaning the electronic device has been finished with the reset operation and is substantively powered on. If the power voltage Vdd rises rapidly (waveform (a)), the voltage A is charged slowly due to the presence of the resistor R. At this time, the output signal POR of the buffer B stays at the low level with a specific time period and then becomes high. Thus, the electronic device is stably reset. However, if the power voltage Vdd rises slowly (waveform (b)) and the voltage of the node A rises almost at the same rate with the power voltage Vdd, the power on reset signal POR does not experience the low level period but stays directly and continuously at the high level. At this time, the electronic device can not be reset normally. If there are positive noises presented on the power voltage Vdd (waveform (c)), the voltage of the node A is instantaneously lower than an input of the buffer B and thus the power on reset signal POR becomes low again. At this time, the electronic device is reset when the user does not intend to reset it. If there are negative noises presented on the power voltage Vdd (also waveform (c)), the capacitor C discharges instantaneously and thus the power on reset signal POR becomes low again when the negative noises disappear from the power voltage Vdd, which does also not meet the requirement of the user.
To solve the above mentioned problem, some electronic components are suggested to be introduced so as to prevent the capacitor C from discharging. One of such power on reset signal generation circuits is shown in FIG. 2A and its signal waveform plot is shown in FIG. 2B. Although failure of the power on reset signal generation due to the noises may be avoided, it is possible to have failure occurred where the power voltage does not substantively experience the reset period.
Therefore, there is a need to provide an improved circuit and method for generating a power on reset signal so that the power on reset signal may be noise-immune and power voltage transition speed and level shift adaptive and thus assured to operate normally.
After a long intensive series of experiments and researches, the inventors finally sets forth such a circuit and method for generating a power on reset signal, which may effectively overcome the demerits existing in the prior art.